1. Field of the Invention
The present invention relates to a method of manufacturing a core-less package substrate, and more particularly, to a method of manufacturing a coreless substrate that is applicable to non-through hole structures, together with a conductive structure of the substrate, so as to increase integration, and simplify manufacture process.
2. Description of Prior Arts
With rigorous development of the electronic industry, the directions of the research in electronic products are turning to high integration and miniaturization to meet the needs for multi-function, high speed, and high frequency. Accordingly, the circuit board for connecting a plurality of active and passive components to circuits is evolving from single layer to multi-layers in order to expand spaces of circuit layout to thereby meet the requirements of high wiring density for integrated circuits.
The conventional processes of electronic devices begin first by providing chip carriers suitable to semiconductor chips, such as substrates or lead frames, then the chip carriers are forwarded to semiconductor packaging industry to proceed with the processes of chip disposing, molding, and ball mounting, etc.; finally, electronic devices having requested functions are produced.
A conventional semiconductor packaging structure is made such that a semiconductor chip is mounted on the top surface of the substrate, and then wire bonding or flip-chip packaging are performed, followed by placing solder balls on the back of the substrate to suffice electrical connections for a printed circuit board. Though high-number leads are achieved in this way, usage on higher frequency and operations at higher speed are restricted due to limited performance of the package structure attributed to lacks of both shorter paths of leads and higher wiring density.
In the method of manufacturing a package substrate, the whole steps of a conventional technique start from providing a core substrate, then drilling, plating, hole-plugging, circuit-forming to thereby accomplish an inner layer structure, and further carrying out a build-up process to obtain a multi-layer carrier substrate. FIGS. 1A to 1E are schematic illustrations of a t prior art. Referring to FIG. 1A about a core substrate 11, a core layer 111 of predetermined thickness has circuit layers 112 formed on the surface thereof. Meanwhile, a plurality of plating through holes 113 are formed in the core layer 111, such that the circuit layers 112 are electrically connected. Subsequently, as shown in FIG. 1B, the core substrate 11 is treated by a build-up process. First, a dielectric layer 12 is formed on the surface of the core substrate 11 with a plurality of openings 13 corresponding to the circuit layers 112. Then, as shown in FIG. 1C, a seed layer 14 as a conductor is formed on the surface of the dielectric layer 12 by electroless plating or sputtering, and a patterned resistive layer 15 is formed on the seed layer 14, having a plurality of open areas 150 therein to thereby expose the parts of the seed layer 14. Subsequently as shown in FIG. 1D, a patterned circuit layer 16 and a plurality of conductive vias 13a are formed in the open areas 150 of the resistive layer 15 by electroplating through the seed layer 14, such that patterned circuit layer 16 is electrically connected to circuit layer 112 through the conductive vias 13a; then the resistive layer 15 is removed and etching is carried out, thereby removing the seed layer 14 covered underneath the resistive layer 15, such that the first built-up structure 10a is formed. Finally, as shown in FIG. 1E, likewise, a second built-up structure 10b is formed on the first built-up structure 10a by the same process, and built-up layers are formed repetitively to thereby obtain a multi-layer substrate.
However, in the process described above, a core substrate is formed by forming circuits on a core layer, followed by a build-up process on the core substrate, thereby forming a multi-layer substrate that complies with the required electrical design. As a result, the thickness of the final multi-layer substrate cannot be reduced, which is unfavorable to the developmental trend of a miniaturized semiconductor package structure. If the thickness of the core substrate is reduced to as thin as 60 μm or less, the manufacture of the multi-layer substrate will be seriously compromised, and the yield from the manufacture of substrates will decrease significantly.
In addition, there are extra steps in the manufacture of the core substrate, such as the hole-plugging and the scrubbing, which increase the manufacture cost. More importantly, it is necessary to form a plurality of plating through holes in the core substrate; the diameter of a typical through hole formed by drilling is approximately 100 μm or more, while the diameter of the conductive via (laser blind hole) is approximately 50 μm. In comparison, the process of plating through holes makes it more difficult to form a structure with finer circuits.
Moreover, in the process of the multi-layer substrate described above, it is necessary to fabricate a core substrate prior to forming dielectric layers and circuit layers, which consequently complicates the manufacture steps, prolongs the process, and increases the manufacture cost.
As a result, the industry urgently needs a solution to avoid the drawbacks of the previous technique, such as the increased thickness of a substrate, low wiring density, low yield, complicated manufacture steps, a lengthy process, and a high manufacture cost.